1. Technical Field
The present invention relates to integrated circuits in general, and in particular to multiplexors. Still more particularly, the present invention relates to a multiplexor having a single event upset immune data keeper circuit.
2. Description of the Prior Art
High-speed static random access memories (SRAMs) typically require a group of special sensing circuits, commonly known as sense amplifiers, to sense and amplify any small signal delivered by a storage cell that is selected for a read operation. While using six-transistor cells as storage cells for data storage, a single-port or multi-port SRAM also use a bitline pair to connect the storage cells to a respective column of sense amplifiers to provide differential sensing. The sense amplifiers are then coupled to a group of multiplexors that employs data keeper circuits for data output from any one of the columns.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a schematic diagram of a multiplexor having a data keeper circuit according to the prior art. As shown, a multiplexor 10 includes a data keeper circuit 14, a p-channel precharge transistor 15, and a series of n-channel input transistors 16a-16n. Data keeper circuit 14 includes a p-channel keeper transistor 11 and an inverter 12. The drain of keeper transistor 11 is connected to the input of inverter 12, and the gate of keeper transistor 11 is connected to the output of inverter 12. Data keeper circuit 14 is also coupled to p-channel precharge transistor 15 and n-channel input transistors 16a-16n. Inputs IN.sub.0 through IN.sub.n are connected to a gate of a corresponding one of input transistors 16a-16n.
During a precharge cycle (i.e., when the clock signal to the gate of transistor 15 is low), a precharge node x is precharged to a logical high state. During an evaluation cycle (i.e., when the clock signal to the gate of transistor 15 is high), inputs IN.sub.0 -IN.sub.n are evaluated and the result appears at the output of multiplexor 10. When the clock signal to the gate of transistor 15 is low again for the next precharge cycle, a logical high state is maintained within data keeper circuit 14.
In order to improve the speed of multiplexor 10, the precharge cycle is often shortened such that the precharge cycle can be completed before the evaluation cycle begins. During this transition period, transistor 15 and input transistors 16a-16n are all turned off, and thus, precharge node x is "floating." As a result, precharge node x becomes very susceptible to single event upsets (SEUs) that may affect the data stored within data keeper circuit 14. The present disclosure provides an improved multiplexor to handle this problem.